Chemical vapor deposition is defined as the formation of a non-volatile solid film on a substrate by the reaction of vapor phase reactants that contain desired components. The gases are introduced into a reactor vessel, and decompose and react at a heated surface on the wafer to form the desired film.
One material commonly chemical vapor deposited is silicon dioxide films. Such is used as an insulating layer between polysilicon and metal layers, between metal layers and multilevel metal systems, as getters, as diffusion sources, as diffusion and implantation masks, as capping layers to prevent out diffusion, and as final passivation layers. In general, the deposited oxide films desirably exhibit uniform thickness and composition, low particulate and chemical contamination, good adhesion to the substrate, low stress to prevent cracking, good integrity for high dielectric breakdown, conformal step coverage for multilayer systems, low pin hole density, and high throughput for manufacturing.
CVD silicon dioxide is an amorphous structure of SiO.sub.4 tetrahedra with an empirical formula SiO.sub.2. Depending on the deposition conditions, CVD silicon dioxide may have lower density and slightly different stoichiometry from thermally grown silicon dioxide, causing changes in mechanical and electrical film properties (such as index of refraction, etch rate, stress, dielectric constant, and high electric-field breakdown strength). Deposition at high temperatures, or use of a separate high temperature post-deposition anneal step, can make the properties of CVD SiO.sub.2 films approach those of thermal oxide. Properties of the finished film can be modified by doping of the deposited layer with compounds such as boron and/or phosphorus.
Interfaces between a deposited SiO.sub.2 layer and silicon create challenges for the semiconductor processor in circuit fabrication. Such interfaces contain various charges and traps which have profound effects on the properties of the electronic components fabricated in the underlying silicon. There are generally four types of charges that exist in the oxide near the Si/SiO.sub.2 interface: a) interface trap charge; b) fixed oxide charge; c) mobile ionic charge; and d) bulk oxide trapped charge. One aspect of this invention is specifically directed to reduction of fixed oxide charge. Such is typically located within 35 Angstroms of the Si/SiO.sub.2 interface, in the so-called "transition region" between silicon and SiO.sub.2. The fixed charge centers are predominantly positive, although some negative compensating senders may also be present. The fixed charge is considered to be a sheet of charge at the Si/SiO.sub.2 interface, and is expressed as the number of charges per unit area (#/cm.sup.2).
CVD SiO.sub.2 processes using organosilicon compounds as precursors have been plagued with creation of excessive fixed charge in the oxide leading to deleterious effects in the underlying devices. In addition, the fixed charge increases almost ten-fold in these films when they are subjected to a high temperature anneal, such as for reflow purposes. Typical methods for reducing fixed charge use ion implantation to control the device threshold voltage, V.sub.t, which is the device parameter most impacted by the fixed oxide charge quantity. It would be desirable to provide CVD SiO.sub.2 processes which minimize resultant fixed charge.
Another challenge in chemical vapor deposition of SiO.sub.2 is in achieving sufficient gap-fill between adjacent conductive runners. Such is also commonly referred to as step coverage where elevation differences occur within the substrate. The problem is illustrated with reference to FIG. 1. Such depicts a semiconductor wafer fragment 10 comprised of a bulk substrate 12, a plurality of conductive metal runners 14, and an overlying deposited layer 16 of CVD SiO.sub.2. Such deposition undesirably produces what is commonly referred to as the "bread-loafing effect" between adjacent runners, which results in voids or keyholes 18 between adjacent runners. It is desirable to achieve complete filling between metal runners such that no voids are present.